1. Field of the Invention
The present invention relates to a scan driving circuit and an organic light emitting display using the same.
2. Discussion of Related Art
In general, an active matrix type display device such as an organic light emitting display includes a pixel array arranged at crossings between data lines and scan lines in a matrix pattern.
The scan lines include horizontal lines (i.e., row lines) of a display region having a matrix of pixels, and sequentially provide a predetermined signal, namely, a scan signal from a scan driving circuit, to the pixel array.
FIG. 1 is a block diagram showing a conventional scan driving circuit. With reference to FIG. 1, the conventional scan driving circuit includes a plurality of stages ST1 to STn, which are dependently coupled with a start pulse SP input line. The plurality of stages ST1 to STn sequentially shift a clock signal C in response to a start pulse SP to generate output signals SO1 to SOn, respectively. In this case, each of second to n-th stages ST2 to STn receives and shifts an output signal of a previous stage as a start pulse.
Accordingly, the stages generate output signals SO1 to SOn in such a way that the start pulse is sequentially shifted, and provide the output signals to the pixel array.
FIG. 2 is a circuit diagram of a stage in the scan driving circuit shown in FIG. 1. FIG. 3 is a timing diagram of the stage shown in FIG. 2. Referring to FIG. 2 and FIG. 3, conventionally, each stage of a scan driving circuit uses a master-slave flip-flop. When a clock CLK is at a low level, such a flip-flop continues to receive an input and maintains a previous output.
In contrast to this, when the clock CLK is at a high level, the flip-flop maintains an input In received at an input terminal when the clock CLK is at the low level, and outputs the received input, but no longer receives the input In.
In the aforementioned circuit, an inverter included in the flip-flop has a problem in that a static current flows when an input thereof is at a low level. Furthermore, in the flip-flop, the number of inverters having received a high-level input is the same number as that of inverters having received a low-level input. Accordingly, the static current flows through a half of all the inverters in the flip-flop, thereby causing power consumption to be increased.
In addition, in the circuit of FIG. 2A, a voltage value due to a ratio of resistance (i.e., transistors M1′ and M2′) connected between a power supply VDD and a ground GND determines a high level of an output voltage OUT. Low level of the output voltage OUT is set to be greater than that of the ground GND by a threshold voltage of the transistor M2′.
By way of example, due to characteristic deviations of the transistors, since levels of an input voltage are different according to respective stages, in the case where the circuit of FIGS. 2 and 2A is used, the deviation occurs when the output voltage is at a high level, with the result that the circuit may be erroneously operated.
Moreover, the deviation in a low level of the output voltage causes a deviation in on-resistance of an input transistor of an inverter included in the circuit of FIG. 2 to occur, thereby weighting a deviation in a high level of the output voltage. In particular, since a panel of an organic light emitting display uses a transistor having a great characteristic deviation, such a problem is more serious.
Further, in the inverter, an electric current flows through an input transistor to charge an output terminal, whereas the electric current flows through a load transistor to discharge the output terminal. Upon a charge of the output terminal, a source-gate voltage of the load transistor is gradually reduced, and a discharge current is accordingly reduced rapidly. This causes the discharge efficiency to be deteriorated.